收藏本站
CAT24C03, CAT24C05
Power ? On Reset (POR)
The CAT24C03/05 incorporates Power ? On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
The CAT24C03/05 device will power up into Standby
mode after V CC exceeds the POR trigger level and will
power down into Reset mode when V CC drops below the
POR trigger level. This bi ? directional POR feature protects
the device against ‘brown ? out’ failure following a
temporary loss of power.
Pin Description
SCL : The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA : The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2 : The Address inputs set the device address
when cascading multiple devices. When not driven, these
pins are pulled LOW internally.
WP : The Write Protect input pin inhibits the write
operations for upper half of memory, when pulled HIGH.
When not driven, this pin is pulled LOW internally.
Functional Description
The CAT24C03/05 supports the Inter ? Integrated Circuit
(I 2 C) Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT24C03/05 acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver.
I 2 C Bus Protocol
The I 2 C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V CC supply via pull ? up
resistors. Master and Slave devices connect to the 2 ? wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is high. An SDA transition while SCL is
HIGH will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake ? up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8 ? bit
serial Slave address. For normal Read/Write operations, the
first 4 bits of the Slave address are fixed at 1010 (Ah). The
next 3 bits are used as programmable address bits when
cascading multiple devices and/or as internal address bits.
The last bit of the slave address, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed. The 3
address space extension bits are assigned as illustrated in
Figure 3. A 2 , A 1 and A 0 must match the state of the external
address pins, and a 8 (CAT24C05) is internal address bit.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge the address byte and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9 th clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.
http://onsemi.com
4
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
CAT24C04ZI-G IC EEPROM SERIAL 4KB I2C 8MSOP
CAT24C05YI-G IC EEPROM SERIAL 4KB I2C 8TSSOP
CAT24C08TDI-GT3 8KB I2C SER EEPROM TSOT 23
CAT24C128HU4IGT3 IC EEPROM 128KB I2C SRL 8UDFN
CAT24C164YI-G IC EEPROM SERIAL 16KB I2C 8TSSOP
CAT24C208WI-GT3 IC EEPROM SER 8KB 400KHZ 8SOIC
CAT24C21LI IC EEPROM SERIAL 1KB DUAL 8PDIP
CAT24C256XI-T2 IC EEPROM 256KBIT 400KHZ 8SOIC
相关代理商/技术参数
CAT24C03WI-G3 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection
CAT24C03WI-GT 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection
CAT24C03WI-GT3 功能描述:电可擦除可编程只读存储器 2K-Bit I2C Serial 电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
CAT24C03WI-T 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection
CAT24C03WIT3 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM
CAT24C03WI-T3 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection
CAT24C03YI-3 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection
CAT24C03YI-G 功能描述:电可擦除可编程只读存储器 (256x8) 2K 1.8 - 5.5 Industrial Temp RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8